The present invention relates to a variable Sigma-Delta modulator which is usable in a receiver for receiving relatively narrowband cellular telephone signals, such as GSM, and relatively wideband cellular telephone signals, such as IS95.
A stable, high order Sigma-Delta modulator is disclosed in EP-A1-0 501 580. The modulator comprises an Nth order low pass filter which is constituted by a series combination of N first-order integrating sections with the output of one section being connected to the input of the next section. Each integrating section comprises an integrator connected in series with a limiter. The individual output signals are tapped-off and weighted by respective weighting amplifiers and added together in a summing stage coupled between the output of the Nth section and the input to an analogue to digital converter (ADC) which is sampled at a fixed rate. An output of the ADC is fed back and subtracted from an input signal, the difference signal being applied to the first section. The gains of the integrating sections and the limiting values of the limiters are selected so that the last or Nth limiter in the series arrangement is activated first when the level in the Sigma-Delta modulator increases, subsequently the last but one or (Nxe2x88x921)th limiter is activated and so on. This reduces the order level of the filter system each time by one when there is an increasing signal level, and causes the Sigma-Delta modulator to remain stable.
It is an object to provide a Sigma-Delta modulator which is adaptable to operate in accordance with telecommunications standards requiring widely differing bandwidths.
According to a first aspect of the present invention there is provided a Sigma-Delta modulator comprising a signal input, a plurality of N integrating stages, where N is an integer of at least 2, a corresponding plurality of summing stages coupled to an input of a respective one of the integrating stages, an output of the first to the (Nxe2x88x921)th summing stages being coupled to an input of the second to the Nth integrating stage, respectively, an analogue to digital converter(ADC) having an input coupled to an output of the Nth integrating stage and an output, a feedback coupling from the ADC to a digital to analogue converter(DAC) which is coupled to an input of each of the summing stages, means for sampling the ADC and DAC, and control means for changing the order of the modulator, said control means comprising means for disconnecting the first of the integrating stages and using the second of the integrating stages as a first of the integrating stages.
According to a second aspect of the present invention there is provided a receiver comprising means for frequency down converting an input signal to an IF signal, bandpass filtering means and a Sigma-Delta modulator comprising a signal input, a plurality of N integrating stages, where N is an integer of at least 2, a corresponding plurality of summing stages coupled to an input of a respective one of the integrating stages, an output of the first to the (Nxe2x88x921)th summing stages being coupled to an input of the second to the Nth integrating stage, respectively, an analogue to digital converter(ADC) having an input coupled to an output of the Nth integrating stage and an output, a feedback coupling from the ADC to a digital to analogue converter(DAC) which is coupled to an input of each of the summing stages, means for sampling the ADC and DAC, and control means for changing the order of the modulator, said control means comprising means for disconnecting the first of the integrating stages and using the second of the integrating stages as a first of the integrating stages.
In one arrangement of the Sigma-Delta modulator made in accordance with the present invention the control means reduces the order of the modulator by disconnecting the first integrating stage from the second summing stage and connecting the signal input to the second summing stage.
In another arrangement of the Sigma-Delta modulator made in accordance with the present invention the control means reduces the order of the modulator by switching the signal input to the second integrating stage to the output of the first summing stage. The sampling rate of the ADC and DAC can be increased thus increasing the bandwidth of the modulator. This particular arrangement and its manner of operation enables the Sigma-Delta modulator to be converted from a higher order, lower bandwidth configuration suitable for use with GSM to a lower order, higher bandwidth configuration suitable for use with IS95.
In reconfiguring the Sigma-Delta modulator made in accordance with the present invention the objective is to enable the product of the dynamic range and the bandwidth appropriate to the specified requirements.
An advantage of reconfiguring the Sigma-Delta modulator by disconnecting/reconnecting the first integrating stage is that significant amounts of power can be saved. This does not impact on the dynamic range because the quantisation noise is higher for a lower order modulator enabling as a result a greater amount of electronic noise to be tolerated.